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d a t a sh eet preliminary speci?cation supersedes data of 1999 jan 05 file under integrated circuits, ic02 1999 nov 12 integrated circuits SAB9081 multistandard picture-in-picture (pip) controller
1999 nov 12 2 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 features double window picture-in-picture (pip) in interlaced or non-interlaced mode at 8-bit resolution internal 1-mbit dram three 8-bit analog-to-digital converters (adcs) (7-bit performance) with clamp circuit for each acquisition channel one pll which generates the line-locked clocks for the subchannel one pll which generates the line-locked clocks for the main and display channels three 8-bit digital-to-analog converters (dacs) linear zoom in both horizontal and vertical directions for the subchannel linear zoom in horizontal direction for the main channel. general description the SAB9081 is a multistandard pip controller which can be used in double window applications. the SAB9081 inserts one or two live video signals with reduced size into another live video signal. the incoming video signals are expected to be analog baseband signals. the conversion to the digital environment is done on chip with adcs. processing and storage of the video data is done entirely in the digital domain. the conversion back to the analog domain is done by dacs. internal clocks are generated by plls which lock on to the applied horizontal and vertical syncs. the main input channel is compressed horizontally by a factor of two and directly fed to the output. after compression, a horizontal expansion of two is possible for the main channel. the subchannel is also compressed horizontally by a factor of two but stored in memory before it is fed to the outputs. quick reference data ordering information symbol parameter conditions min. typ. max. unit supply v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.0 3.3 3.6 v i ddd digital supply current - 50 - ma i dda analog supply current 140 165 210 ma pll f clk(sys) system clock frequency 1792 f hsync - 28 - mhz b loop loop bandwidth - 4 - khz t jitter short-term stability peak-to-peak jitter for 64 m s -- 4ns z damping factor - 0.7 - type number package name description version SAB9081h qfp100 plastic quad ?at package; 100 leads (lead length 1.95 mm); body 14 20 2.8 mm sot317-2
1999 nov 12 3 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... block diagram handbook, full pagewidth mgm836 73 88 93 44 43 45 46 47 scl 74 sda t7 t6 tclk tm tcbc tcbd tcbr 75 por test control pkoff 69 fbl 68 dac and buffer dy 8 dv 10 du 12 v bias(da) 9 v ref(t)(da) 11 v ref(b)(da) 13 shsync 87 svsync 72 su 79 sv 81 sy v bias(sa) v ref(t)(sa) v ref(b)(sa) 83 84 82 80 dhsync 94 dvsync 70 mu 2 my 98 mv v bias(ma) v ref(t)(ma) v ref(b)(ma) 100 97 99 1 pll and clock generator dclk 71 t5 to t0 32 to 37 tc 38 pll and clock generator clamp and adc clamp and adc line memory internal dram display control horizontal and vertical filter horizontal filter 89 34 90 91 92 95 21 to 29, 31, 52 to 60 96 v dda(mf) v ssa(ma) 56 v dda(ma) v dda(da) 714 v ssa(da) v ddd(da) 15 16 v ssd(da) v ssd(p1) 17 20 v ddd(p1) v ddd(rp) 39 40 v ddd(rl) v ssd(rl) 41 42 v ssd(rm) v ddd(rm) 61 64 v ssd(rp) v ddd(p2) 65 66 v ssd(p2) v ssd(d) 67 76 v ddd(d) v dda(sa) 77 78 v ssa(sa) v dda(sf) 85 86 v ssd(sa) v ddd(sa) SAB9081 v ssd(ma) v ddd(ma) n.c. v dda(dp) v ssa(dp) v ssa(sp) v dda(sp) i 2 c-bus control 6 19 v ssd(t1) and v ssd(t2) v ssd(t4) to v ssd(t7) v ssd(t8) and v ssd(t9) 18, 19 48 to 51 62, 63 v ssd(t3) 30 4 2 fig.1 block diagram.
1999 nov 12 4 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 pinning symbol pin type description v ref(b)(ma) 1 i/o analog bottom reference voltage for main channel adcs mu 2 i analog u input for main channel v dda(mf) 3 s analog supply voltage for main channel front-end buffers v ssa(ma) 4 s analog ground for main channel adcs v dda(ma) 5 s analog supply voltage for main channel adcs v dda(da) 6 s analog supply voltage for dacs v ssa(da) 7 s analog ground for dacs dy 8 o analog y output of dac v bias(da) 9 i/o input/output analog bias reference voltage for dacs dv 10 o analog v output of dac v ref(t)(da) 11 i/o input/output analog top reference voltage for dacs du 12 o analog u output of dac v ref(b)(da) 13 i/o analog bottom reference voltage for dacs v ddd(da) 14 s digital supply voltage for dacs v ssd(da) 15 s digital ground for dacs v ssd(p1) 16 s digital ground for periphery v ddd(p1) 17 s digital supply voltage for periphery v ssd(t1) 18 s digital ground for test v ssd(t2) 19 s digital ground for test v ddd(rp) 20 s digital supply voltage for memory periphery n.c. 21 to 29 - not connected v ssd(t3) 30 s digital ground for test n.c. 31 - not connected t5 32 i/o test data input/output bit 5 (cmos levels) t4 33 i/o test data input/output bit 4 (cmos levels) t3 34 i/o test data input/output bit 3 (cmos levels) t2 35 i/o test data input/output bit 2 (cmos levels) t1 36 i/o test data input/output bit 1 (cmos levels) t0 37 i/o test data input/output bit 0 (cmos levels) tc 38 i test control input (cmos levels) v ddd(rl) 39 s digital supply voltage for memory logic v ssd(rl) 40 s digital ground for memory logic v ssd(rm) 41 s digital ground for memory core v ddd(rm) 42 s digital supply voltage for memory core tclk 43 i test clock input (cmos levels) tm 44 i test mode input (cmos levels) tcbd 45 i test control block data input (cmos levels) tcbc 46 i test control block clock input (cmos levels) tcbr 47 i test control block reset input (cmos levels) v ssd(t4) to v ssd(t7) 48 to 51 s digital ground for test
1999 nov 12 5 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 n.c. 52 to 60 - not connected v ssd(rp) 61 s digital ground for memory periphery v ssd(t8) and v ssd(t9) 62 and 63 s digital ground for test v ddd(p2) 64 s digital supply voltage for periphery v ssd(p2) 65 s digital ground for periphery v ssd(d) 66 s digital ground for digital core v ddd(d) 67 s digital supply voltage for digital core fbl 68 o fast blanking control signal output (cmos levels; +5 v tolerant) pkoff 69 o peak off control signal output (cmos levels; +5 v tolerant) dvsync 70 i vertical sync display channel input (cmos levels; +5 v tolerant) dclk 71 i test clock input (28 mhz; cmos levels) svsync 72 i vertical sync for subchannel input (cmos levels; +5 v tolerant) scl 73 i/o input/output serial clock (i 2 c-bus; cmos levels; +5 v tolerant) sda 74 i/o input/output serial data/acknowledge output (i 2 c-bus; +5 v tolerant) por 75 i power-on reset input (cmos levels; pull-up resistor connected to v dd ) v dda(sa) 76 s analog supply voltage for subchannel adcs v ssa(sa) 77 s analog ground for subchannel adcs v dda(sf) 78 s analog supply voltage for subchannel front-end buffers and clamps su 79 i analog u input for subchannel v ref(b)(sa) 80 i/o input/output analog bottom reference voltage for subchannel adcs sv 81 i analog v input for subchannel v ref(t)(sa) 82 i/o input/output analog top reference voltage for subchannel adcs sy 83 i analog y input for subchannel v bias(sa) 84 i/o analog bias reference voltage for subchannel adcs v ssd(sa) 85 s digital ground for subchannel adcs v ddd(sa) 86 s digital supply voltage for subchannel adcs shsync 87 i horizontal sync input for subchannel (v i 1999 nov 12 6 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 fig.2 pin configuration. handbook, full pagewidth 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v ref(b)(sa) su v dda(sf) v ssa(sa) v dda(sa) por sda scl svsync dclk dvsync pkoff fbl v ddd(d) v ssd(d) v ssd(p2) v ddd(p2) v ssd(t9) v ssd(t8) v ssd(rp) n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. v ssd(t7) v ref(b)(ma) mu v dda(mf) v ssa(ma) v dda(ma) v dda(da) v ssa(da) dy v bias(da) dv v ref(t)(da) du v ref(b)(da) v ddd(da) v ssd(da) v ssd(p1) v ddd(p1) v ssd(t1) v ssd(t2) v ddd(rp) n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. v ssd(t3) n.c. t5 t4 t3 t2 t1 t0 tc v ddd(rl) v ssd(rl) v ssd(rm) v ddd(rm) tclk tm tcbd tcbc tcbr v ssd(t4) v ssd(t5) v ssd(t6) mv v ref(t)(ma) my v bias(ma) v ssd(ma) v ddd(ma) dhsync t7 v dda(dp) v ssa(dp) v ssa(sp) v dda(sp) t6 shsync v ddd(sa) v ssd(sa) v bias(sa) sy v ref(t)(sa) sv 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mgm837 SAB9081
1999 nov 12 7 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 functional description acquisition the internal pixel rate is 28 mhz for the y, u and v channels. it is expected that the bandwidth of the input signals will be limited to 4.5 mhz for the y input and 1.125 mhz for the u and v inputs. inset synchronisation is achieved via the acquisition hsync and vsync pins of the main channel. the display is driven by the main channel clock. the starting-point of the acquisition can be controlled with the acquisition fine positioning added to a system constant. with a nominal input f hsync and standard ntsc signals, 1408 samples (active video) are acquired and processed by the SAB9081. here, the nominal input f hsync results in a nominal system clock frequency of 1792 f hsync (approximately 28 mhz). pip modes fig.3 pip modes. handbook, full pagewidth mgm810 main replay main sub sub main sub i 2 c-bus description the i 2 c-bus provides bidirectional 2-line communication between different ics. the sda line is the serial data line and the scl the serial clock line. both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. the SAB9081 has the i 2 c-bus address 2ch. valid subaddresses are 00h to 18h; register 15h (except bits 7 and 6) and registers 16h to 18h are reserved for future extensions. i 2 c-bus control is according to the i 2 c-bus protocol: first, a start sequence must be put on the i 2 c-bus. then, the i 2 c-bus address of the circuit must be sent, followed by a subaddress. after this sequence, the data of the subaddresses must be sent. an auto-increment function gives the option of sending data of the incremented subaddresses until a stop sequence is sent. table 1 gives an overview of the i 2 c-bus addresses. the data bits that are not used should be set to zero.
1999 nov 12 8 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 table 1 overview of i 2 c-bus addresses for a description of the various data bits, see the following pages. sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h mpipon spipon s1fld sfreeze dnonint pipmode2 pipmode1 pipmode0 01h shblow1 shblow0 shred5 shred4 shred3 shred2 shred1 shred0 02h svblow svred6 svred5 svred4 svred3 svred2 svred1 svred0 03h bgvfp3 bgvfp2 bgvfp1 bgvfp0 bghfp3 bghfp2 bghfp1 bghfp0 04h sdhfp7 sdhfp6 sdhfp5 sdhfp4 sdhfp3 sdhfp2 sdhfp1 sdhfp0 05h sdvfp7 sdvfp6 sdvfp5 sdvfp4 sdvfp3 sdvfp2 sdvfp1 sdvfp0 06h -------- 07h -------- 08h mahfp3 mahfp2 mahfp1 mahfp0 sahfp3 sahfp2 sahfp1 sahfp0 09h savfp7 savfp6 savfp5 savfp4 savfp3 savfp2 savfp1 savfp0 0ah duvpol dvspol dfpol dhsync suvpol svspol sfpol shsync 0bh mainfidpos7 mainfidpos6 mainfidpos5 mainfidpos4 mainfidpos3 mainfidpos2 mainfidpos1 mainfidpos0 0ch subfidpos7 subfidpos6 subfidpos5 subfidpos4 subfidpos3 subfidpos2 subfidpos1 subfidpos0 0dh bgon bon mfidpon sfidpon prio algoff sfblkpkoff1 sfblkpkoff0 0eh bsel1 bsel0 sbbrt1 sbbrt0 - sbcol2 sbcol1 sbcol0 0fh dpal spal slsel5 slsel4 slsel3 slsel2 slsel1 slsel0 10h i2chold sv1 sdsel5 sdsel4 sdsel3 sdsel2 sdsel1 sdsel0 11h mdhfp7 mdhfp6 mdhfp5 mdhfp4 mdhfp3 mdhfp2 mdhfp1 mdhfp0 12h mdvfp7 mdvfp6 mdvfp5 mdvfp4 mdvfp3 mdvfp2 mdvfp1 mdvfp0 13h mhblow sv2 mhred5 mhred4 mhred3 mhred2 mhred1 mhred0 14h - vbwidth2 vbwidth1 vbwidth0 sv3 hbwidth2 hbwidth1 hbwidth0 15h dntsc sntsc all bits are reserved 16h to 18h all bits are reserved
1999 nov 12 9 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 mpipon ( double window ) bit mpipon is used to switch the main channel pip on (logic 1) or off (logic 0). spipon bit spipon is used to switch the subchannel pips on (logic 1) or off (logic 0). p rio the priority bit decides whether the main channel pip (prio set to logic 0) or the subchannel pip (prio set to logic 1) will be on top when both pips overlap. s1fld if s1fld is set to logic 0, two fields are used for the live pip. when a 50/60 hz or a 60/50 hz mode is detected, the SAB9081 automatically switches to the 1-field mode (1-field resolution vertically). if s1fld is set to logic 1, only one field is used. this causes joint line errors but saves memory. this bit should not be set in normal modes. sf reeze with sfreeze set to logic 1, the current live subchannel pip will be frozen. if set to logic 0, it is unfrozen. a lg o ff in double window mode, precautions are taken to prevent a joint line error. under some conditions, this feature should be switched off. this can be realized by setting this bit to logic 1. normally, bit algoff should be set to logic 0. bit sv3, when set to logic 0, can overrule bit algoff. it is recommended to set sv3 to logic 1. dn onint in normal mode (this bit is logic 0), the SAB9081 calculates whether a signal is non-interlaced and reacts accordingly. with bit dnonint set to logic 1, the display channel is forced into the non-interlaced mode. in the non-interlaced mode, only one field is used during the processing of the pips. p ip m ode bits pipmode<2:0> determine the pip modes for the SAB9081, as shown in table 2. table 2 pip modes shr ed and svr ed ( double window ) bits shred<5:0> and svred<6:0> determine the reduction factors in the double window mode. the horizontal reduction is equal to shred/96; the vertical reduction is equal to svred/96. shred should lie in the range from 0 to 48; if set to logic 0, the pip is off. svred should lie in the range from 0 to 96; if set to logic 0, the pip is off. when the horizontal reduction factor is 48/96, 704 samples are processed. the horizontal reduction is linear; therefore, when it is 24/96, 352 samples are processed. the same holds for the vertical reduction factor but then with the number of lines. for ntsc, the number of processed lines can be calculated from svred/96 228 lines; for pal, this is svred/96 276 lines. shr ed and svr ed ( replay ) in the replay mode, the ranges of shred and svred are limited as follows: shred = 12; svred = 24, 16 or 12. this leads to a fixed horizontal reduction factor of 1 8; and to a variable vertical reduction factor of 1 4, 1 6 or 1 8 . note that the resulting replay pip can be expanded by using bits shblow and/or svblow. bgh fp and bgv fp these bits control the horizontal and vertical positioning of the pip configuration on the screen. the horizontal range is adjustable in 16 steps of four 28 mhz clock periods. the vertical range is 16 steps of 1 line/field. the background colour can be adjusted with bits bsel, sbbrt and sbcol. sdh fp and sdv fp these bytes control the horizontal and vertical positioning of the subchannel pips on the screen. the horizontal range is 256 steps of eight 28 mhz clock periods. the vertical range is 256 steps of 1 line/field. pipmode<2:0> mode 000 double window mode 001 replay mode
1999 nov 12 10 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 mah fp , sah fp and sav fp bits mahfp<3:0>, bits sahfp<3:0> and byte savfp control the horizontal and vertical inset starting-points of the acquired data. the horizontal range is 16 steps of eight 28 mhz clock periods when sv2 is set to logic 1. when sv2 is set to logic 0, the horizontal range is restricted to eight steps. the vertical range is 256 steps of 1 line/field. duvp ol , dvsp ol , dfp ol and dh sync these bits control the pll/deflection settings. with duvpol, the polarity of the border uv signals can be inverted when the deflection circuit after the SAB9081 expects inverted signals. with dvspol set to logic 0, the SAB9081 triggers on positive edges of the dvsync. if dvspol is set to logic 1, it triggers on negative edges. dfpol can invert the field id of the incoming fields. bit dhsync determines the timing of the dhsync pulse. if it is set to logic 0, a burstkey is expected; if it is set to logic 1, a horizontal sync is expected at pin dhsync. suvp ol , svsp ol , sfp ol and sh sync these bits control the pll/decoder settings. with suvpol, the polarity of the video uv signals can be inverted when the decoder circuit before the SAB9081 emits inverted signals. with svspol set to logic 0, the SAB9081 triggers on positive edges of the svsync. if it is set to logic 1, it triggers on the negative edges. sfpol can invert the field id of the incoming fields. bit shsync determines the timing of the shsync pulse. if it is set to logic 0, a burstkey is expected; if it is set to logic 1, a horizontal sync is expected at pin shsync. mf id po n and sf id po n bits mfidpon (main field identification position on) and sfidpon (subfield identification position on) enable the field identification position fine tuning. the default value is off (logic 0), no fine positioning. when on (logic 1), the field identification position is determined by the value of bytes mainfidpos and subfidpos. bgo n bit bgon determines whether the background is visible. the background has a size of 720 pixels and 240 lines for ntsc and 720 pixels and 288 lines for pal. the background colour can be adjusted with bits bsel, sbbrt and sbcol. bo n , sbb rt , sbc ol and bs el bit bon can switch the sub-borders on (logic 1) or off (logic 0). bits sbbrt<1:0> and sbcol<2:0> set the brightness and colour type of the selected border. the brightness is set in four levels of 30%, 50%, 70% and 100% ire. the colour type is one of black (grey), blue, red, magenta, green, cyan, yellow or white (grey). for black and white, a finer scale is available. bsel selects which colour is set, background or border, see table 3. table 3 bsel modes mdh fp and mdv fp these bytes control the horizontal and vertical positioning of the main pip on the screen. the horizontal range is 256 steps of eight 28 mhz clock periods. the vertical range is 256 steps of 1 line/field. mhr ed bits mhred<5:0>, in a range from 0 to 48, determine the horizontal reduction factor mhred/96. if they are set to logic 0, the pip is off. if they are set to the maximum value of 48, the horizontal reduction factor is 0.5. shb low and svb low ( replay mode ) bits shblow<5:0> and bit svblow are used in the replay mode. these bits can expand a pixel on the display side by a factor two (01) or four (11) in the horizontal direction (shblow) and a factor of two (1) in the vertical direction (svblow). zero values indicate no expansion. mhb low bit mhblow can expand the main picture by a factor of two in the horizontal direction. sls el ( replay mode ) in the replay pip mode, bits slsel<5:0> determine at which memory location the pip data is written, the range depends on the memory usage for each pip. the maximum number of pips that can be stored in ntsc mode is 42. bsel<1:0> border colour set 00 main 01 sub 10 background 11 sub-border select
1999 nov 12 11 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 sds el ( replay mode ) bits sdsel<5:0> select which pip is read from memory. valid numbers are dependent on the maximum value of slsel. dp al and sp al in normal operation (dpal and spal are logic 0), the SAB9081 calculates from the number of incoming lines whether the signal is ntsc (< 288 lines) or pal ( 3 288 lines). if dpal is set to logic 1, the main window is sized to 276 lines. if dpal is set to logic 1 and the subchannel is still ntsc, the subchannel picture will be smaller than the main channel picture (difference of approximately 40 lines). if spal is set to logic 1, the subchannel is forced to pal mode and 276 lines are acquired instead of 228 in ntsc mode. dntsc and sntsc in normal operation (dntsc and sntsc are logic 0), the SAB9081 calculates from the number of incoming lines whether the signal is ntsc (< 288 lines) or pal ( 3 288 lines). if dntsc is set to logic 1, the main window is sized to 228 lines. if dntsc is set to logic 1 and the subchannel is still pal, the subchannel picture will be larger than the main channel picture (difference of approximately 40 lines). if sntsc is set to logic 1, the channel is forced to ntsc mode and 228 lines are acquired instead of 276 in pal mode. sfb lk p k o ff bits sfblkpkoff<1:0> shift signals fbl and pkoff with respect to the yuv output, by half pixels, see table 4. table 4 shifts of fbl and pkoff sfblkpkoff<1:0> shift of fbl and pkoff 00 no shift 01 +0.5 pixel 10 - 0.5 pixel 11 - 1 pixel i2ch old bit i2chold controls the updating of the i 2 c-bus controlled function towards the pip. if set to logic 1, some updates are on hold until the bit is set to logic 0. at the next main vsync, all settings are passed to the pip functions. the bits and bytes that are on hold when the i2chold bit is set to logic 1 are: mpipon, spipon, dnonint and pipmode shblow and svblow shred and svred bghfp and bgvfp sdhfp and sdvfp shpic and svpic bgon, bon and prio bsel, sbbrt and sbcol sdsel mdhfp and mdvfp hbwidth and vbwidth. sv1 bit sv1 controls the internal horizontal offset of the background. when set to logic 0, the offset is 0.86 m s; when set to logic 1, the offset is 4.56 m s. sv2 bit sv2, when set to logic 0, limits the range of the mahfp and sahfp parameters. otherwise (bit sv2 set to logic 1), the parameters have their maximum range (which is recommended). sv3 bit sv3, when set to logic 0, can overrule bit algoff when the main channel is ntsc and the subchannel is pal. in this particular case, bit algoff is always set to logic 0 internally. otherwise (bit sv3 set to logic 1), bit algoff is never overruled. it is recommended to set sv3 to logic 1.
1999 nov 12 12 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 hbw idth and vbw idth bits hbwidth<2:0> and vbwidth<2:0> control the horizontal and vertical border sizes in steps of two pixels and one line. the default horizontal border size is four pixels and the vertical border size is two lines per field. default means after power-up and no i 2 c-bus data sent to the pip controller. n otes 1. when the input signals for the main and/or subchannel are non-interlaced, joint line errors can occur. when non-interlaced signals are input, the SAB9081 switches automatically to the non-interlaced mode. 2. when the prevent joint line error algorithm is switched off (algoff is set to logic 1), joint line errors can still occur in the 2-field mode. 3. when a pal signal is applied to the main channel and an ntsc signal is applied to the subchannel, the subchannel will automatically enter the 1-field mode. now, a joint line error can occur. in the pal/ntsc mode, the subpicture will be smaller than the main picture (difference of approximately 40 lines). 4. when an ntsc signal is applied to the main channel and a pal signal is applied to the subchannel, the subchannel will automatically enter the 1-field mode. now, a joint line error can occur. in the ntsc/pal mode, the subpicture will be larger than the main picture (difference of approximately 40 lines). acquisition channel adcs and clamping the analog input signals are converted to digital signals by three adcs per channel. the resolution of the adcs is 8 bits (dnl is 7 bits and inl is 6 bits) and the sampling is performed at the system clock frequency of 28 mhz for the y input. a bias voltage (v bias ) is used to decouple the ac components on internal references. the inputs should be ac coupled and an internal clamp circuit (using external clamp capacitors) will clamp the input to a level derived internally from v ref(b)(ma/sa) for the luminance channels and, for the chrominance channels, to (v ref(t)(ma/sa) + v ref(b)(ma/sa) )/2 + lsb/2. the clamping starts at the active edge of the burst key. internal video buffers amplify the standard y, u and v input signals to the correct adc levels. pll the pll generates an internal system clock of 1792 f hsync , from the hsync, which is approximately 28 mhz. dacs and video buffers the 28 mhz digital video signals are fed to the 8-bit dacs that produce the required analog video signals. the video buffers amplify these signals prior to being fed to the output to drive another device.
1999 nov 12 13 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 limiting values in accordance with the absolute maximum rating system (iec 134). quality specification in accordance with snw-fq-611, part e , dated 14 december 1992. esd levels the standard esd specification is jedec class ii (2 kv human body model, 200 v machine model) unless indicated otherwise. table 5 esd performance symbol parameter min. max. unit v dd supply voltage range - 0.5 5.0 v t stg storage temperature - 25 +150 c t amb ambient temperature 0 70 c v esd electrostatic discharge handling - 2kv r th(j-a) thermal resistance - 45 k/w p max maximum power dissipation - 1.0 w pin symbol human body model (v) machine model (v) 68 fbl 1000 standard speci?cation 69 pkoff 1000 70 dvsync 1000 72 svsync 1000 73 scl 1000 74 sda 1000 rest in range 1 to 17 all other pins standard speci?cation rest in range 64 to 100
1999 nov 12 14 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 analog characteristics v dda = 3.3 v; v ddd = 3.3 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v dda positive supply voltage 3.0 3.3 3.6 v v ssa ground voltage - 0 - v d v dda(max) maximum dc difference between supply voltages - 0 100 mv d v ssa(max) maximum dc difference between ground voltages - 0 100 mv i ddd(q) quiescent current of digital supply voltages note 1 - 050 m a i dda(dp) display pll supply current - 0.4 - ma i dda(sp) sub pll supply current - 0.4 - ma i dda(ma) main adcs supply current note 2 60 70 90 ma i dda(sa) sub adcs supply current note 2 60 70 90 ma i dda(da) dacs supply current 8 10 12 ma i dda(mf) main buffers supply current 4 6 9 ma i dda(sf) sub buffers supply current 4 6 9 ma i dda(tot) total analog supply current note 2 140 165 210 ma i ddd(tot) total digital supply current - 50 - ma analog-to-digital converter and clamping v ref(t) top reference voltage note 3 2.70 2.82 2.95 v v ref(b) bottom reference voltage note 3 0.95 1.07 1.20 v v iy(p-p) y input signal amplitude (peak-to-peak value) note 4 - 1.00 1.04 v v i(v)(p-p) v input signal amplitude (peak-to-peak value) note 4 - 1.05 1.10 v v i(u)(p-p) u input signal amplitude (peak-to-peak value) note 4 - 1.33 1.38 v i i input current clamping off - 0.1 -m a clamping on - 55 -m a c i input capacitance - 5 - pf f sample sample frequency note 5 - 1792 f hsync - khz res resolution 8 8 8 bit dnl differential non-linearity - 1.4 - +1.4 lsb inl integral non-linearity - 2.0 - +2.0 lsb a cs channel separation - 48 - db v clamp(y) y clamping voltage level note 6 1.25 1.34 1.45 v v clamp(u,v) u/v clamping voltage level note 7 1.80 1.93 2.15 v
1999 nov 12 15 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 notes 1. digital clocks are silent, input pins por and tm are connected to v dda . 2. this value is measured with an external bias resistor of 39 k w , resulting in a bias current of 55 m a. 3. voltages v ref(t) and v ref(b) are made by a resistor division of v dda . they can be calculated with the formulas: and . 4. the input signals are amplified to meet an internal peak-to-peak voltage level of 0.8 (v ref(t) - v ref(b) ), which equals the internal adc input range. 5. the internal system clock frequency is 1792 f hsync of the input channel. 6. the y clamp level is not equal to the v ref(b) of the adcs. 7. the uv channels are clamped to: . 8. the internal system clock frequency is 1792 f hsync of the main channel. digital-to-analog converter and output stage v ref(t) top reference voltage 1.10 1.20 1.30 v v ref(b) bottom reference voltage 0.15 0.23 0.30 v r l load resistance 1 - 1000 k w c l load capacitance 0 - 5pf f sample sample frequency note 8 - 1792 f hsync - khz res resolution 8 8 8 bit dnl differential non-linearity - 1.0 - +1.0 lsb inl integral non-linearity - 1.0 - +1.0 lsb a cs channel separation - 48 - db display pll and clock generation f i(pll) input frequency ntsc 14 15.75 17 khz pal 14 15.625 17 khz sub pll and clock generation f i(subpll) input frequency ntsc 14 15.75 17 khz pal 14 15.625 17 khz symbol parameter conditions min. typ. max. unit v ref(t) v dda 2.82 v dda(nom) ------------------------- v = v ref(b) v dda 1.07 v dda(nom) ------------------------- v = v ref b () v ref t () v lsb ++ 2 ----------------------------------------------------------- -
1999 nov 12 16 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 digital characteristics v dda = 3.3 v; v ddd = 3.0 to 3.6 v; t amb = 0 to 70 c; unless otherwise speci?ed. notes 1. the absolute maximum input voltage is 6.0 v. 2. x is the source/sink current under worst case conditions. x is reflected in the name of the i/o cell according to the drive capability. minimum value of x is 1 ma. 3. the internal system clock frequency is 1792 f hsync of the main channel and subchannel. symbol parameter conditions min. typ. max. unit dc characteristics v ih high-level input voltage default 0.8v ddd - v ddd + 0.5 v pin 74 0.8v ddd - 5.5 (1) v 5 v tolerant pins 68, 69, 70, 72, 73 0.8v ddd - 5.5 (1) v v il low-level input voltage default - 0.5 - 0.2v ddd v v hys hysteresis voltage 0.8 -- v v oh high-level output voltage i oh = - x ma; v ddd = 3.0 v; note 2 0.85v ddd -- v v ol low-level output voltage i ol = x ma; v ddd = 3.0 v; note 2 -- 0.4 v i ol = 2 ma; v ddd = 3.0 v -- 0.4 v |i li | input leakage current v i =0v -- 1 m a v i =v ddd -- 1 m a |i oz | 3-state output leakage current v o = 0 v or v o =v ddd -- 1 m a i lu(i/o) i/o latch-up current v < 0 v; v > v ddd 200 -- ma r pu internal pull-up resistor 16 33 78 k w ac characteristics f clk(sys) system clock frequency note 3 - 1792 f hsync - khz t r rise time - 625ns t f fall time - 625ns
1999 nov 12 17 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 test and application information figure 4 gives the application diagram in a standard configuration. input signals main channel cvbs and subchannel cvbs from different video sources are processed by the SAB9081 and inserted by the yuv to rgb switch. fig.4 application diagram. handbook, full pagewidth mgl572 subchannel cvbs sub decoder tda8310 main decoder tda8310 SAB9081 pip controller yuv yuv fbl yuv to rgb switch tda4780 yuv/rgb processing and deflection circuit rgb main channel cvbs hs/vs rgb hs/vs yuv hs/vs yuv hs/vs
1999 nov 12 18 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.40 0.25 0.25 0.14 14.1 13.9 0.65 18.2 17.6 1.0 0.6 7 0 o o 0.15 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot317-2 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 0.8 0.4 d e q e a 1 a l p detail x l (a ) 3 b 30 c b p e h a 2 d z d a z e e v m a 1 100 81 80 51 50 31 pin 1 index x y b p d h v m b w m w m 0 5 10 mm scale qfp100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot317-2 a max. 3.20
1999 nov 12 19 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 nov 12 20 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
1999 nov 12 21 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1999 nov 12 22 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 notes
1999 nov 12 23 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9081 notes
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20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 printed in the netherlands 545004/25/02/pp 24 date of release: 1999 nov 12 document order number: 9397 750 06137

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